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- Yamaha 6388 VPDC
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- 3C2h (R): Misc Output Register
- bit 2-3 Select Master Clock
- 0 Use CLK0 as Master Clock (Usually 25.175 MHz)
- 1 Use CLK1 as Master Clock (Usually 28.322 MHz)
- 2 Use CLK2 as Master Clock (Usually external)
- 3 Use CLK3 as Master Clock (Usually the panel clock)
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- 3d4h index 72h (R/W): Video Control
- bit 0 Display on monochrome monitor/flat panel using
- Hatching for G/H code 7 if set, Gray scale if not.
- 1 Enable Gray Scale/Hatching generator
- 2 Enable Tonal Gradation if set.
- 3 Select one of 2 16 word by 6 bit Color Palettes.
- 4 Enable 64 colors on 8 color panel if set.
- 5 This bit is output at the CON pin.
-
- 3d4h index 73h (R/W): Hatching Select
- bit 0 Use Hatching for G/H code 8 if set, Gray Scale if not.
- 1 Use Hatching for G/H code 9 if set, Gray Scale if not.
- 2 Use Hatching for G/H code 10 if set, Gray Scale if not.
- 3 Use Hatching for G/H code 11 if set, Gray Scale if not.
- 4 Use Hatching for G/H code 12 if set, Gray Scale if not.
- 5 Use Hatching for G/H code 13 if set, Gray Scale if not.
- 6 Use Hatching for G/H code 14 if set, Gray Scale if not.
- 7 Use Hatching for G/H code 15 if set, Gray Scale if not.
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- 3d4h index 74h (R/W): Vertical Adjust
- bit 0-7 Number of non-used lines at the top of the screen.
- For Dual Panel Single Drive use (Number of blank lines at
- the top-1)*2.
- For other types use (number of blank lines at the top)-1.
-
- 3d4h index 75h (R/W): Raster Scan Control
- bit 0-1 Line Repeat Cycle.
- 0 5 line cycle
- 1 6 line cycle
- 2 7 line cycle
- 3 8 line cycle
- 2-4 Raster Scan Correction for Dual Panels
- Set to LRC-(NLUS-NVA) mod LRC -1.
- LRC is 3d4h index 75h bit 0-1.
- NLUS is 3d4h index 78h-79h Number of Lines on Upper Screen.
- NVA is 3d4h index 74h Number of Vertical adjustments.
- Note: The Multi Raster Scan defined in this and the next register is
- used if 3d4h index 9 bit 7 is clear.
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- 3d4h index 76h (R/W): Raster Scan Data
- bit 0-7 Raster Scan Data. A clear bit indicates that the next scanline
- should be repeated, whereas a set bit increments the line counter.
- The bits are rotated in a 5, 6, 7 or 8 bit cycle depending on
- 3d4h index 75h bit 0-1.
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- 3d4h index 77h (R/W): LC Adjust
- bit 0-4 Latch Clock Adjust. Number of dots times to add to
- Start and End Blanking times, as plasma and EL
- panels require strict timings.
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- 3d4h index 78h (R/W): Vertical Screen Size H
- bit 0 Bit 8 of the Vertical Screen Size.
- The lower 8 bits are in 3d4h index 79h.
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- 3d4h index 79h (R/W): Vertical Screen Size L
- bit 0-7 Vertical Screen Size bit 0-7. Bit 8 is in 3d4h index 78h.
- For full screen panels this value is the number of lines
- on the display-1 typically 479.
- For Dual Panel Single Drive types use (number of lines in
- each panel-1)*2 typically 478.
- For Dual Panel Dual Drive types use (number of lines in
- each panel-1) typically 239.
-
- 3d4h index 7Ah (R/W): Horizontal Screen Size
- bit 0-7 Horizontal Screen Size. For Dual Panel Dual Drive types
- this is (number of dots per line)/4 -1 typically 159.
- For other types this is (number of dots per line)/8 -1
- typically 79.
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- 3d4h index 7Bh (R/W): M Signal Pulse Width H
- bit 0-1 Bits 8-9 of the M Signal C ontrol.
- Lower 8 bits are in 3d4h index 7Ch.
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- 3d4h index 7Ch (R/W): M Signal Pulse Width L
- bit 0-7 Bits 0-7 of the M Signal Control.
- Bits 8-9 are in 3d4h index 7Bh bits 0-1.
- This sets the cycle time for reversing the polarity of
- the AC conversion signal M which is transmitted to the
- LCD panel.
- This is a way of controlling the brightness of the display.
-
- 3d4h index 7Dh (R/W): Panel Control
- bit 0-1 Selects Panel Screen type.
- 0 1 Screen Panel
- 1 2 Screen Single Drive type
- 2 2 Screen Dual Drive type.
- 2-3 Selects number of bits to transfer for each pixel.
- 0 = 1 bit serial, 1 = 4 bit parallel and 2 = 8 bit parallel.
- 4 If set the Shift Clock is output constantly, otherwise
- only during display intervals.
- 6 If set FLM is output 2 cycles delayed from VSYNC,
- if clear they are simultaneous.
- 7 If set the cursor blinks at a field cycle of 32, 16 if not.
-
- 3d4h index 7Eh (R/W): Stand By
- bit 0 If set VPDC functions are stopped and Stand-by mode is
- entered. Operation is resumed when this bit is cleared.
- If DRAMs are used for Video RAM the content of display
- memory will be lost in Stand-by mode.
- 1 If set writing of the Configuration Switches Register
- (3d4h index 7Fh) from the CPU is enabled.
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- 3d4h index 7Fh (R/W): Configuration Switches
- bit 0-3 Display Type
- 4-5 Panel/CRT connection
- 0 VGA CRT (analog) connected
- 1 EGA CRT (digital) connected
- 2 or 3 Flat panel connected
- 6 SRAM is used if set, DRAM else
- 7 Scratch
-
- 3d4h index 80h..FFh (R/W): Color Map Registers.
- bit 0-3 Color Map for color #((index#-80h)*2)
- 4-7 Color Map for color #((index#-80h)*2+1)
- Note: index 80h contains color #0 and 1, index 81h color #2 and 3 et cetera.
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- Grey Scale/Hatching
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- The Yamaha 6388 VPDC can support both analog, digital and
- various panel, plasma and LCD displays.
- In order to display original color information on displays
- with limited colors (monochrome, 8, 16 or 64 colors/shades)
- some conversions must be made.
- The VPDC has a Color Mapping Table (CMT) which converts
- the 8bit color signal to 4 bits.
- This 4 bit code is either used directly for output
- or sent through a Grey Scale/Hatching (G/H) converter.
-
- G/H Code Gradation Hatching
- 0 ---- OFF ----
- 1 ---- 1/3 ----
- 2 ---- 2/3 ----
- 3 ---- ON ----
- 4 ---- 1/4 ----
- 5 ---- 2/4 ----
- 6 ---- 3/4 ----
- 7 1/5 1,3/4
- 8 2/5 2,0/4
- 9 3/5 2,4/4
- 10 4/5 1/3 Hatch
- 11 1/6 2/3 Hatch
- 12 5/6 3\1 Hatch
- 13 2/7 3\2 Hatch
- 14 3/7 2|3 Hatch
- 15 4/7 1/2 Hatch
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- ID Yamaha VGA:
-
- if testinx2($3d4,$7c,$7c) then YAMAHA_6388
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